Integrated circuit devices such as dynamic random access memory (DRAM) devices typically utilize well region biasing techniques to improve electrical characteristics of devices therein by increasing latch-up immunity, increasing cell isolation and increasing operating speed. Unfortunately, such biasing techniques may lead to an increase in short channel effects which can degrade device performance. Techniques to improve the electrical characteristics of discrete devices within a DRAM device are disclosed in Korean Laid-open Patent Publication No. 94-003026 and in U.S. Pat. No. 5,595,925 to Chen et al. The Korean Laid-open Patent Publication No. 94-003026 discloses a semiconductor memory device comprising a substrate of first conductivity type (e.g., P-type), a first well region of second conductivity (to which a first bias (Vint) is applied) in the substrate and a second well region of first conductivity (to which a second bias (Vss/Vbb) is applied) in the first well region. A third well region of second conductivity (to which the second bias Vss/Vbb is applied) is also provided in the substrate, at a location adjacent the first well region. The '925 patent to Chen et al. also discloses a DRAM device having three separate regions: an input/output section 12, a peripheral transistor section 14 and a memory array section 16 all formed on a P-type substrate layer 18. The DRAM device of the '925 patent can employ separate substrate bias voltages for each section. The input/output section 12 has a P-type region 22 that is isolated from the P-type substrate layer 18 by an N-type well region 20. The peripheral transistor section 14 also has a P-type region 36 that can be isolated from the P-type substrate layer 18 by an optional N-type well region 40 for those devices which require a different substrate bias voltage between the peripheral transistor section 14 and the memory array section 16.
Referring now to FIG. 1, a cross-sectional view of a triple-well integrated circuit memory device according to the prior art is illustrated. In particular, this memory device comprises a first N-type well region 104 formed in a memory array region 140 of a P-type substrate 102, a first P-type sub-well region 106 formed in the first N-type well region 104, first N-type source and drain regions 108 which are formed in the first P-type sub-well region 106, a first gate electrode 110 extending opposite the first P-type sub-well region 106, and a first P-type contact region 112 in the first P-type sub-well region 106. The first P-type contact region 112 is electrically connected to a back bias terminal Vbb. The first N-type well region 104 also includes P-type source and drain regions 114 and an N-type contact region 118 which is coupled to a positive power supply terminal Vcc. A second gate electrode 116 is also provided opposite the first N-type well region 104. In the peripheral circuit region 146, an NMOS region 142 and a PMOS region 144 are provided. The NMOS region 142 includes a second P-type well region 120 in the P-type substrate 102. N-type source and drain regions 122 are also provided in the second P-type well region 120 along with a P-type contact region 126 which is electrically connected to a ground reference terminal Vss. An insulated gate electrode 124 is also provided opposite the second P-type well region 120. The PMOS region 144 includes a second N-type well region 128, and P-type source and drain regions 130 in the second N-type well region 128. An insulated gate electrode 132 is also provided on the substrate 102, opposite the second N-type well region 128. An N-type contact region 134 is also provided in the second N-type well region 128 and is electrically connected to a power supply terminal Vcc. A P-type contact region 136 is also provided in the P-type substrate 102 and is electrically connected to the ground reference terminal Vss.
Referring now to FIG. 2, an electrical schematic of an integrated circuit memory device according to the prior art is provided. This memory device includes first and second memory cell regions 202 and 218, first and second equalization circuits 204 and 216, first and second isolation gates 206 and 214, first and second sense amplifiers 208 and 212 and a column select circuit 210 which is electrically coupled to complementary data lines IO and IOB. Peripheral circuits 220 are also provided in a second P-type well region and a second N-type well region which are electrically coupled to the ground terminal Vss and the power supply terminal Vcc, respectively. As illustrated, left and right word lines WLL and WLR, left and right equalization control signal lines PEQL and PEQR, left and right isolation control signal lines PISOL and PISOR, complementary amplifier control signal lines LA and LAB and a column select signal line CSL are provided to the memory device. Furthermore, with respect to FIG. 1, the memory cells 202 and 218, the equalization circuits 204 and 216, the isolation gates 206 and 214, the second sense amplifier 212 and the column select circuit 210 contain NMOS transistors which are all formed in the first P-type sub-well region 106. This P-type sub-well region 106 is electrically coupled to the back bias terminal Vbb. On the other hand, the first sense amplifier, which comprises PMOS transistors, is formed in the first N-type well region 104 which is electrically coupled to the power supply terminal Vcc.
Notwithstanding these memory devices which contain multiple well regions and sub-well regions which inhibit short channel effects, increases in integration density may lead to an undesirable increase in parasitic body effects. To inhibit such body effects, a ground voltage can be used as a substrate voltage in the peripheral circuit region instead of a negative voltage bias. However, such techniques to reduce body effects may not lead to an improvement in noise immunity.